ESD-Induced Circuit Performance Degradation in RFICs

ESD structures have inevitable parasitic impacts on circuit performance. This paper reports results of an investigation into ESD-induced circuit performance degradation in RFICs including clock corruption, reduced slew rate, narrowed bandwidth, and noise generation. Performance degradation of ~80%, ~30% & ~5% were observed in clock, Op Amp and LNA circuits studied, which were recovered substantially by using novel compact ESD structures that are critical to reducing ESD influences on circuits while maintaining adequate ESD performance. Introduction ESD protection for RFIC applications is becoming a new design challenge because of the substantial interactions between the ESD protection structures and the circuits protected. On one hand, the circuit-to-ESD influences exit that often leads to premature ESD failures – a well-studied ESD topic. On the other hand, the ESD-to-circuit influences are inevitable, which may substantially degrade circuit performance. This under-studied topic gets more attention in RF and VDSM IC design recently. The main ESD-to-circuit impacts include RC effect of ESD-induced capacitance (CESD) and ESD-related noises. Such ESD-induced parasitic effects become intolerable to high frequency applications. Considering that a complete ESD protection solution requires multiple ESD devices for each I/O pin to against ESD pulses of all modes: i.e., I/O-to-VDD positively (PD) & negatively (ND), I/O-to-ground (GND) positively (PS) & negatively (NS), and power clamps [1, , the overall ESDinduced parasitic might substantially corrupt the circuit performance. It is imperative to develop novel compact ESD protection structures with low ESD parasitics for highfrequency applications. In this work, ESD-to-circuit influences of different ESD devices on several RF IC chips, e.g., a GHz ring-oscillator, a high-performance Op Amp, and a low noise amplifier (LNA) circuit, were investigated. ESD Design and Measurements This work compares the conventional MOS ESD structure (ESD1) with two new ESD structures (ESD2 & ESD3) 3] for the same ESD performance level, ESDV = 4KV HBM. I. ESD1: MOS ESD structures Fig. 1 illustrates a conventional MOS ESD structure. Normally, GGNMOS and GGPMOS devices are used to protect I/O pins against all ESD pulses (PD. ND, PS, & NS) as shown in Fig.1a. Fig. 1b is a typical NMOS cross-section showing parasitic junction capacitance. Only Cgd and Cdb have effects in GGNMOS as modeled in Fig. 1c. Both NMOS and PMOS ESD structures contribute to the overall parasitic capacitance, CESD. From ESD simulation, four 200μm-wide NMOS fingers were needed for 4KV protection, as confirmed by HBM zapping. Simulation and measurement data match well as shown in Table I. II. ESD2: A New Dual-Direction ESD Structure Ideally, an ESD protection unit should provide lowimpedance current shunting-channels formed by active devices in all ESD stressing modes. However, in the NMOS ESD structure, only one active discharging-path is formed by a NPN device, with a parasitic diode serving as a Ishunting path in the opposite direction that often limits the ESD performance, which cannot be used for VDD>5V because 10% ∆VDD may turn on the diode accidentally. A new dual-direction ESD structure (ESD2) [3] was designed to address this problem as illustrated in Fig. 2. Briefly, ESD2 is a two-terminal (A & K), five-layer (N1P2N3P4N5) structure consists of one lateral PNP (Q1=P2N3P4), two vertical NPN (Q2=N1P2N3 & Q3=N3P4N5) and four parasitic resistors, R1, R2, R3, & R4. The structure forms two functional SCR units: unit 1= Q1-Q2 and unit 2= Q1-Q3. In operation, when a positive ESD pulse appears at A (w.r.t. K), BC junction (N3P4) of Q1 is reverse biased to its breakdown and the generated holes are collected by the negative terminal K via P4-P layer. VBE (P4N5) of Q3 increases and eventually turns on Q3. The SCR unit 1 is therefore triggered off (at Vt1) and driven into deep snapback region (holding voltage Vh ≤2V). An active I-path with negligible RON is thereby formed to shunt ESD current and clamp the I/O pad voltage at Vh. After the ESD pulse is over, the thyristor is quickly discharged and then turned off when the current decreases to below its holding current level. Similarly, the SCR unit 2 operates during a negative ESD pulse event (K w.r.t. A). Hence this forms a dual -direction ESD protection device. Data from simulation and measurements are in Table I. A 50μm device passed HBM ESDV=4KV and a 200μm device passed 14KV (test limit). Compared to the MOS ESD1, the ESD2 features dual-polarity operation and smaller size. Therefore, ESD2 has much lower CESD as shown in Table I, which greatly reduces the capacitive effects on the circuits. However, two ESD2's are still needed for each I/O pin for I/O-to-VDD and I/O-to-Gnd, respectively. In addition, one extra power clamp is needed. Hence sizable CESD still exists, especially for high-pin-count circuits. III. ESD3: A New All-Direction ESD Structure ESD3 is a new all-direction ESD protection structure [4] with three terminals (A, K1, & K2) and eight layers (N1, P2, N3, P4,